First, a 1:1 phone interview, then an on-site interview.
In the on-site interview, there were three technical interviews separately in the morning, followed by lunch with the manager.
In the afternoon, there was another technical interview and then a discussion with the manager's manager.
The first interviewer asked about bus connection verification, specifically the protocols of AHB and AXI. They then inquired about the number of VIPs to be used in the verification environment. I initially misunderstood the question, as using real CPUs and their code wouldn't require replacing interfaces with VIPs. However, if the CPU itself needed replacement, only other slave/master interfaces would require VIPs. After clarification, the interviewer's intent was to replace all CPU and other IP interfaces with VIPs.
The second interviewer asked two questions:
The third interviewer asked the following:
The last technical interviewer asked:
There was another question I forgot who asked: Use SystemVerilog to generate addresses with the following constraints: 0x0 (mem1), 0x4 (mem2), 0x8 (mem3), 0xC (mem1), 0x10 (mem2), 0x14 (mem3), and so on.
The following metrics were computed from 1 interview experience for the Qualcomm SoC Verification Engineer role in Raleigh, North Carolina.
Qualcomm's interview process for their SoC Verification Engineer roles in Raleigh, North Carolina is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Qualcomm's SoC Verification Engineer interview process in Raleigh, North Carolina.