Challenging job. Great work environment.
Tight delivery schedule some time.
The process is relatively simple, consisting mostly of aptitude questions that test basic logical and mathematical reasoning. Additionally, there are a few questions on data structures, covering fundamental concepts like arrays, linked lists, and ba
Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Overall, it was a good and new experience. I answered almost all the questions, ranging from basic inquiries to project-related ones. The interview level was moderate, and it was a nice experience.
The process is relatively simple, consisting mostly of aptitude questions that test basic logical and mathematical reasoning. Additionally, there are a few questions on data structures, covering fundamental concepts like arrays, linked lists, and ba
Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Overall, it was a good and new experience. I answered almost all the questions, ranging from basic inquiries to project-related ones. The interview level was moderate, and it was a nice experience.