Will be able to wake up after working here, and you can understand politics very well.
No career growth for senior and lead engineers.
No work-life balance, strictly.
Downsize the directors and senior directors. They are eating more than the hard-working engineers.
Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Total 4 rounds. 1. Digital design basics like sequence detector, Flip-flops. 2. SI and PDN basics like crosstalk, power delivery network, crosstalk, jitter. 3. Most difficult issue solved. 4. HR round.
There were five technical rounds. Each round focused on a different topic: * GPU architecture concepts * Graphics pipeline in-depth discussion * System design problems with implementation in your choice of programming language.
Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Total 4 rounds. 1. Digital design basics like sequence detector, Flip-flops. 2. SI and PDN basics like crosstalk, power delivery network, crosstalk, jitter. 3. Most difficult issue solved. 4. HR round.
There were five technical rounds. Each round focused on a different topic: * GPU architecture concepts * Graphics pipeline in-depth discussion * System design problems with implementation in your choice of programming language.