Good compensation, but extremely high workload
Good compensation, but extremely high workload
Good compensation and accessibility to a lot of technical resources with industry-best EDA software and tools.
Extremely high workload, no time for learning. You'll always be in a get-work-done-at-all-cost mode.
Late nights and frequent weekend work should be expected.
All teams are running lean on resources, so don't expect much collaboration or peer learning within the team, as all would be working on different items.
Work-life balance should be the norm, not work-life effectiveness as you're currently marketing. Learning and innovation happen only when people have free time in their workdays to sit back, think, and dive deep into things. When a truckload of items is dumped on a team, everyone will be in survival mode, just getting work done and nothing else.
Additional Ratings
Was this helpful?
Qualcomm Interview Questions
Qualcomm Interview Experiences
Senior Lead Engineer
There were five technical rounds. Each round focused on a different topic: * GPU architecture concepts * Graphics pipeline in-depth discussion * System design problems with implementation in your choice of programming language.
Senior Lead Engineer
Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Senior Lead Engineer
Total 4 rounds. 1. Digital design basics like sequence detector, Flip-flops. 2. SI and PDN basics like crosstalk, power delivery network, crosstalk, jitter. 3. Most difficult issue solved. 4. HR round.
Senior Lead Engineer
Bengaluru, Karnataka, IndiaJanuary 1, 2023There were five technical rounds. Each round focused on a different topic: * GPU architecture concepts * Graphics pipeline in-depth discussion * System design problems with implementation in your choice of programming language.
Senior Lead Engineer
Bengaluru, Karnataka, IndiaSeptember 30, 2024Project related technical discussion. Technical discussion in SystemVerilog UVM, protocol knowledge. Given some coding questions. Puzzle questions. Verilog, SystemVerilog, UVM, AXI protocol-based questions. Project architecture and interface signals.
Senior Lead Engineer
Bengaluru, Karnataka, IndiaJanuary 1, 2016Total 4 rounds. 1. Digital design basics like sequence detector, Flip-flops. 2. SI and PDN basics like crosstalk, power delivery network, crosstalk, jitter. 3. Most difficult issue solved. 4. HR round.
