Good job and good work.
Nothing in specific, good condition.
There was only one technical round, and I got selected. They asked me to draw waveforms and write coverage classes for AHB, along with assertions about AHB. Then, they asked basic SystemVerilog and UVM questions. They covered all the basics in SV and
The process comprised 4-5 interview panels, each with different expertise. Each panel included one manager and one technical authority and lasted approximately 30 to 45 minutes. Questions were straightforward, rather than graded questions where the
The process was rigid. The first round was an aptitude cum technical online test, and then there were two tech rounds and one HR round. They mainly focused on basics, especially digital logic design, some puzzles, and basic C.
There was only one technical round, and I got selected. They asked me to draw waveforms and write coverage classes for AHB, along with assertions about AHB. Then, they asked basic SystemVerilog and UVM questions. They covered all the basics in SV and
The process comprised 4-5 interview panels, each with different expertise. Each panel included one manager and one technical authority and lasted approximately 30 to 45 minutes. Questions were straightforward, rather than graded questions where the
The process was rigid. The first round was an aptitude cum technical online test, and then there were two tech rounds and one HR round. They mainly focused on basics, especially digital logic design, some puzzles, and basic C.