Independent Work, Toxic Culture
Independent Work, Toxic Culture
If you prefer to work independently, and I mean really top of your work, then it's a place for you. Also, if you work in some niche area with specific expertise rather than more generalized/evergreen dev work, then it's very good. Compensation is decent, but there is no parity in comps; you can land on any side of the pay spectrum.
I have worked in two different teams in SW and HW. A lot of managers are awful and have lower technical skills. Real talented people are also humble, so if you are lucky enough to be in such a team, then it's good.
There is no collaborative environment here; the irony is it's in their so-called "core values". People are always trying to take credit for your work because of the regress annual review process. I'll say there are more cunning and toxic people than I expected.
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Qualcomm Interview Experiences
Verification Engineer
Mostly focuses on SystemVerilog and UVM basics, plus some basic C & puzzles. It covers mostly fundamental concepts, and the interview level is moderate. Focus on the basics of: * CMOS * Verilog * SystemVerilog * UVM * Analog CMOS
Verification Engineer
SV, UVM, your projects, scripting, and puzzles are important. Design questions can cover digital electronics, computer architecture, and other areas. All topics are important. Have in-depth knowledge. Whatever you mention on your resume will be as
Verification Engineer
There was only one technical round, and I got selected. They asked me to draw waveforms and write coverage classes for AHB, along with assertions about AHB. Then, they asked basic SystemVerilog and UVM questions. They covered all the basics in SV and
Verification Engineer
Bengaluru, Karnataka, IndiaApril 1, 2025Mostly focuses on SystemVerilog and UVM basics, plus some basic C & puzzles. It covers mostly fundamental concepts, and the interview level is moderate. Focus on the basics of: * CMOS * Verilog * SystemVerilog * UVM * Analog CMOS
Verification Engineer
Bengaluru, Karnataka, IndiaJune 20, 2024SV, UVM, your projects, scripting, and puzzles are important. Design questions can cover digital electronics, computer architecture, and other areas. All topics are important. Have in-depth knowledge. Whatever you mention on your resume will be as
Verification Engineer
Bengaluru, Karnataka, IndiaApril 1, 2021There was only one technical round, and I got selected. They asked me to draw waveforms and write coverage classes for AHB, along with assertions about AHB. Then, they asked basic SystemVerilog and UVM questions. They covered all the basics in SV and
