There were four rounds:

• Written
• Technical
• HR

Written Test:

The written test was an online test consisting of separate Aptitude (Logical, English, Quantitative) and Technical rounds.

Technical questions covered RC, RL, RLC circuits, steady-state response, and transient analysis. Basic questions on MOSFETs, thresholds, pass transistors, 8085 instructions, computer architecture basics, and basic digital concepts based on counters, FSMs, and MUXes were also included. Simple questions on STA were asked.

Technical Round 1:

I was asked to give a briefing of my resume. They then asked questions on the projects that they found interesting.

Q: Given the pattern below, draw the FSM for the same (consider ABC as a word): A: …010… B: …110… C: …111…

Q: What are the types of scaling?

Q: Explain the effects of each scaling on MOSFETs in every aspect with reasoning.

Q: Define Setup Time and Hold Time. Explain the reasons behind setup and hold time.

Q: Write Verilog code to generate a clock with a 70% duty cycle.

Q: Give the duty cycle of the clock for these Verilog codes: i. always begin #70 clk=0; #30 clk=1; end ii. always begin #70 clk<=0; #30 clk<=1; end iii. always begin clk=#70 0; clk=#30 1; end iv. always begin clk<=#70 0; clk<=#30 1; end

Q: One logical question based on statistics.

Technical Round 2:

Q: Describe the concept of sequential circuits and combinational circuits.

Q: Given a vending machine accepting Rs. 5 coins only, with coffee costing Rs. 15 only. Would the machine be based on sequential or combinational logic? Explain.

Q: Given a router with 2GB of data and four output buses of size 32-bit each. The router must send its data one by one on each of the four buses such that the first destination gets the first 128 bits, the second destination gets the next 128 bits, and so on, in a cyclic manner. Write pseudocode for this process.

Q: Explain the difference between fork-join, fork-join any, and fork-join none.

Q: Explain the functions and differences between $monitor and $display; $stop and $finish.

Q: Given a memory whose bus lines 10 and 14 have been interconnected, how would you detect this fault?

Q: One logical question.