The first round was a written test, consisting of aptitude, Verilog, SystemVerilog, and basics of electronics like CMOS and EDA. The written test was medium to tough, with 35 MCQs and 5 subjective questions. The subjective questions were based on Verilog and static timing analysis.
SystemVerilog, UVM, Verilog constraints and assertions, about projects
The following metrics were computed from 1 interview experience for the Siemens Verification Engineer role in Bangalore Rural, Karnataka.
Siemens's interview process for their Verification Engineer roles in Bangalore Rural, Karnataka is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Siemens's Verification Engineer interview process in Bangalore Rural, Karnataka.