Phone screen only.
What is in a lib and lef file?
How is a clock cell different than a standard cell?
How to speed up a timing path?
What is clock latency?
Physical design related questions, such as timing, area, and power.
The following metrics were computed from 1 interview experience for the SpaceX Senior ASIC Engineer role in Sunnyvale, California.
SpaceX's interview process for their Senior ASIC Engineer roles in Sunnyvale, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for SpaceX's Senior ASIC Engineer interview process in Sunnyvale, California.