ASIC Design Engineer - Pixel IP
Description For ASIC Design Engineer - Pixel IP
Apple's Hardware Technologies group is seeking an ASIC Design Engineer to join their Pixel IP design team. This role focuses on designing next-generation, high-performance, power-efficient system-on-chips (SoCs) that power Apple's beloved devices.
As an ASIC Design Engineer, you'll be at the heart of crafting and implementing sophisticated pixel processing engines that help deliver breathtaking images and video across Apple's product line. You'll work in a highly collaborative environment, interfacing with multiple teams including chip integration, physical design, power, logic design, and verification.
The role combines deep technical expertise in ASIC design with system-level thinking. You'll be responsible for integrating large pixel-processing subsystems using SystemVerilog, implementing complex memory addressing schemes, and managing critical aspects like power domains and clock management. Your work will directly impact millions of customers through the performance and efficiency of Apple's devices.
Key technical areas include front-end ASIC implementation, logic synthesis, timing analysis, and power optimization. You'll need to balance performance requirements with power efficiency while working within physical design constraints. The role requires both technical depth in digital design and strong collaboration skills to work effectively across teams.
This is an opportunity to work on cutting-edge hardware technology at one of the world's most innovative companies. You'll be part of a team that pushes the boundaries of what's possible in mobile and consumer electronics, while maintaining Apple's high standards for quality and user experience. The role offers competitive compensation, comprehensive benefits, and the chance to make a significant impact on products used by millions of people worldwide.
Responsibilities For ASIC Design Engineer - Pixel IP
- Integration of large pixel-processing subsystems using SystemVerilog
- Writing detailed micro-architectural specifications
- Performing front-end implementation including logic synthesis and timing analysis
- Working with Physical Design teams for floorplanning and timing closure
- Collaborating with teams to improve performance while minimizing power and area
- Working with verification teams to debug and verify functionality
Requirements For ASIC Design Engineer - Pixel IP
- BS and a minimum of 3 years relevant industry experience
- Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog
- Experience in ASIC implementation, synthesis, timing analysis
- Experience with system design methodologies with multiple clock domains
- Knowledge of low-power design issues and UPF power intent specification
- Familiarity with common on-chip bus protocols (AMBA)
- Knowledge of ASIC/FPGA design methodology and scripting languages
- Excellent written and verbal communication skills
Benefits For ASIC Design Engineer - Pixel IP
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Education reimbursement
- Discretionary bonuses
- Relocation assistance
