CAD Engineer - RTL Construction
Description For CAD Engineer - RTL Construction
Join Apple Silicon group as a CAD Engineer focusing on RTL Construction. In this hands-on role, you'll utilize your CAD experience to support Design and DFT teams, writing and supporting software to create and compile new RTL for integration into Apple's designs. You'll work with cutting-edge technology, focusing on memory bist, scan codec, power, and other functionalities. As part of a tight-knit team with decades of experience, you'll collaborate closely with customers to automate solutions into reality and production.
The role is crucial in maintaining Apple Silicon's vision of creating high-quality flows for chip production. You'll develop checkers for design analysis, create RTL manipulation methods, and ensure their correctness. Your responsibilities include system evangelization, documentation creation, and continuous customer engagement for workflow improvement.
Working with an energized CAD team, you'll contribute to Apple's comprehensive chip design efforts. The position offers opportunities to work with leading industry methods, create elegant solutions to complex challenges, and directly impact Apple's renowned products. Your work will help ensure Apple products can efficiently handle tasks that make them beloved by millions.
Responsibilities For CAD Engineer - RTL Construction
- Developing and supporting checkers to analyze designs for specific topologies or structures
- Developing and supporting new methods of editing or manipulating RTL
- Evangelizing and promoting systems across all Apple Silicon design teams
- Creating documentation and providing training to internal customers
- Contributing in development within the Front-End Infrastructure space
- Engaging with internal customers for workflow improvement
- Supporting Apple's chip design efforts
Requirements For CAD Engineer - RTL Construction
- Bachelors Degree +3 years of relevant industry experience
- Experience in programming languages such as Perl or Python
- Experience in Verilog/System Verilog
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