Cellular ASIC Methodology Engineer

Apple is seeking a Cellular ASIC Methodology Engineer to join their Hardware Technologies group. This role focuses on developing and optimizing design and implementation methodology for integrated circuits across multiple areas including area efficiency, power optimization, and design technology co-optimization.

The position involves working with advanced process technologies (3nm, 2nm and beyond) to design innovative products at both block/IP-level and system-level. The engineer will be responsible for establishing design guidelines, developing EDA tool flows, and driving timing convergence improvements across design teams.

Key responsibilities include physical design optimization, analysis and validation of designs, power and performance optimization, and collaboration with multiple functional teams. The role requires expertise in VLSI design flows, strong programming skills, and the ability to work with various EDA tools and methodologies.

The ideal candidate will have extensive experience with SoC power flows, design technology co-optimization, and the ability to identify and solve scaling bottlenecks in new technology nodes. They should be capable of performing comprehensive analysis of design databases and silicon validation data to improve overall design metrics.

This position offers competitive compensation including base pay between $171,600 and $302,200, plus additional benefits such as stock options, comprehensive medical coverage, and educational reimbursement. The role is based in San Diego and requires working with cross-functional teams to deliver next-generation, high-performance, power-efficient cellular chips and system-on-chips (SoC).

At Apple, you'll be part of a team that's committed to innovation and excellence, working on products that impact millions of users worldwide. The company offers a collaborative environment where individual contributions are valued and there are numerous opportunities for professional growth and development.