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Formal Verification Engineer

A leading technology company that designs and manufactures consumer electronics, software, and services.
Senior Software Engineer
In-Person
5,000+ Employees
10+ years of experience
Hardware

Job Description

Apple's Silicon Technologies group is seeking a Formal Verification Engineer to join their world-class team. This role is crucial in designing and manufacturing next-generation, high-performance, power-efficient processors and system-on-chip (SoC). As part of this position, you'll work at the center of SoC design verification efforts, collaborating with design teams to ensure Apple products and services can seamlessly handle tasks that make them beloved by millions.

The role involves comprehensive formal verification for various design blocks and IPs, including CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, and more. You'll work closely with Security Enclave design engineers, develop formal micro-architecture specifications, and create comprehensive verification test plans with a focus on security requirements.

Key aspects include proving design properties, identifying bugs, and implementing optimized formal models. You'll be responsible for crafting innovative solutions for security attack modeling and developing reusable verification code bases. The position requires expertise in VLSI, digital logic design, and formal verification technologies, along with strong debugging and interpersonal skills.

This is an opportunity to work with the best Formal Verification team in the world, making a critical impact on delivering high-quality functional products to millions of customers. The role combines technical expertise with creative problem-solving, ensuring the robustness and security of complex design micro-architectures that power Apple's cutting-edge devices.

Last updated a day ago

Responsibilities For Formal Verification Engineer

  • Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification
  • Developing comprehensive formal verification test plan that includes unique security requirement verification
  • Proving properties of the design, finding design bugs, and working closely with design teams
  • Crafting novel and creative solutions for modelling security attacks
  • Developing and implementing re-usable and optimized formal models and verification code base
  • Architecting correct-by-construction design methodologies

Requirements For Formal Verification Engineer

  • BS degree and a minimum of 10 years of relevant industry experience in silicon validation, silicon design, software engineering, or a related field
  • Hands on experience with VLSI and digital logic design and verification techniques
  • Knowledge and experience in interpreting hardware specifications
  • Proficiency in any scripting language with excellent debugging skills
  • Temporal logic assertion-based languages such as SVA or PSL

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