Silicon Validation Engineer

Responsible for handling and completing the post silicon validation and characterization test plans across Process, Voltage and Temperature (PVT). Debug various issues encountered along the way such as setup artifacts, test code, logic bugs, and physical design debugs. Understand new chip features and define coverage applicable to test environment. Execute a validation test on large volume and analyze results such as pass, failure, artifacts and surprises. Responsible for being the first line of defense for failure isolation, and work with domain experts to define debugs and come up with a root cause. Assist in driving a fix for the root cause. Maintain and create automation scripts and flows for self-consumption. Summarize debugs and analyze along the line of improvements in both DFX features and test coverage!