SoC Physical Design Verification Engineer

Apple's Silicon Technologies group is seeking a SoC Physical Design Verification Engineer to join their team in crafting next-generation, high-performance, power-efficient processors and system-on-chip solutions. This role is integral to Apple's mission of creating products that enrich people's lives.

As a Physical Design Verification Engineer, you'll be part of a critical team responsible for ensuring the quality and reliability of complex SOC designs. You'll work with cutting-edge technology, performing various types of physical verification checks including LVS, DRC, ANT, and ESD at both chip and block levels. Your expertise will be crucial in collaborating with CAD/Technology teams for flow validation and working closely with implementation teams throughout the chip design cycle.

The position offers the opportunity to work on groundbreaking technology that powers millions of Apple devices worldwide. You'll be involved in padring, bump, and RDL design, working directly with package and floorplan teams. Your role will be highly visible and impactful, requiring both technical expertise and leadership skills as you manage schedules and support cross-functional engineering efforts.

The ideal candidate brings a strong background in electrical or computer engineering, with proven experience in physical verification flows and methodology through tape out execution. You'll need comprehensive knowledge of ASIC physical design, place and route design flow methodology, and proficiency with industry-standard tools like Mentor Calibre and Synopsys ICV.

Join Apple's Silicon Technologies group to be part of a team that's pushing the boundaries of what's possible in processor design and contributing to products used and loved by millions of people worldwide.