ASIC Digital Design Verification Engineer
Description For ASIC Digital Design Verification Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Staff Digital Design Verification Engineer to join their team in San Francisco Bay Area. This role requires extensive experience in ASIC Design Verification, with a focus on System Verilog, UVM, and verification coverage matrix. The ideal candidate will have 8+ years of experience with a BSc or 6+ years with an MS in Electrical/Computer Engineering.
The position offers a competitive compensation package ranging from $119,000 to $190,000 annually, plus discretionary bonuses and equity opportunities. The role involves working with cutting-edge technologies including ARM core, various bus protocols, and serial peripherals, requiring expertise in both hardware and software aspects of verification.
This is an excellent opportunity for a seasoned professional looking to work with advanced semiconductor technologies. The role combines technical expertise with leadership opportunities, requiring strong communication skills and the ability to influence project outcomes. Broadcom offers comprehensive benefits including medical, dental, vision coverage, 401(k) matching, ESPP, and various leave benefits.
The company culture promotes innovation, technical development, and collaborative problem-solving. This position is perfect for someone who wants to work at the forefront of semiconductor technology while being part of a global technology leader that values diversity and professional growth.
Requirements For ASIC Digital Design Verification Engineer
- BSc in Electrical Engineering or Computer Engineering with 8+ years of experience or MS with 6+ years of experience
- Deep knowledge of System Verilog, UVM and verification coverage matrix
- Experience in developing checker, scoreboard & writing assertions
- Knowledge of ARM core, APB/AHB bus protocol, Serial peripherals
- Experience with randomized vectors for analog and digital behavioral model verification
- Knowledge of standard industry EDA tools - Synopsys/Cadence
- Working knowledge of Assembly, C, and C++ languages
- Experience with GLS, zero delay & non-zero delay parasitic annotated simulations
- Strong written and verbal communication skills
- Excellent time and task management skills
Benefits For ASIC Digital Design Verification Engineer
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual bonus
- Equity compensation
