DFT Engineer
Job Description
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a senior DFT (Design for Testability) Engineer to join their team in San Jose, CA. This role offers an exciting opportunity to work on cutting-edge connectivity products in the high-speed data center networking space.
The position requires a highly qualified professional with advanced education (MS or PhD) in Electrical or Computer Engineering and substantial experience in ASIC DFT development. You'll be working with state-of-the-art technologies and tools, including scan insertion, boundary scan, MBIST, and Logic BIST, while handling complex multi-clock domain architectures operating at speeds up to 2GHz.
This is an excellent opportunity for a seasoned professional looking to make significant contributions to advanced semiconductor development. The role offers competitive compensation ($120,000 - $192,000) plus additional benefits including equity, annual bonus, and comprehensive healthcare coverage. You'll be working with a collaborative team in a company known for innovation in the semiconductor industry.
The ideal candidate will combine technical expertise with strong communication skills and a collaborative approach to problem-solving. This role provides an excellent platform for career growth within a leading global technology company, working on projects that directly impact the future of data center networking and connectivity solutions.
Responsibilities For DFT Engineer
- Contributing to highly integrated connectivity products
- DFT architecture development
- Working with high-speed data center networking technologies
Requirements For DFT Engineer
- MS or PhD in Electrical Engineering or Computer Engineering
- 6+ years of experience in ASIC DFT development for serial high-speed data center networking
- Experience as a DFT architect for chip and block level IPs
- Understanding of Scan insertion, scan coverage, Boundary scan, fault simulation, MBIST, Logic BIST, JTAG
- Experience with scan stitching, data uncompression/compression and tap controller
- Experience with Genus or similar DFT tools for synthesis scripts and constraints generation
- Familiarity with high speed DFT design rules (~2GHz) and multi clock domain architectures
- Experience with ATPG tools to generate verilog and ATE vectors and cross verification
- Experience with GLS and timing analysis
- Experience with silicon bring-up & debug, memory and scan diagnostics
- Strong written and verbal communication skills
- Proactive, collaborative and creative approach
Benefits For DFT Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity compensation
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