High Speed RTL Design Engineer
Job Description
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a High Speed RTL Design Engineer to join their team in San Jose, CA. This senior-level position requires expertise in high-speed DSP SerDes RTL design and offers a competitive salary range of $120,000 - $192,000 plus additional benefits.
The role demands a minimum of 6 years of experience and an advanced degree (MS or PhD) in Electrical or Computer Engineering. The successful candidate will work on cutting-edge technology, developing high-speed ADC based SerDes RTL designs and implementing PAM4 DSP based SerDes systems. This includes working with equalization, adaptation, and high-speed ADC calibration.
Key responsibilities include designing and developing RTL for high-speed serial interconnect architectures, particularly focusing on 100G/200G per lane PAM4 systems. The role requires proficiency with industry-standard front-end tools and experience with advanced TSMC process nodes (7nm-2nm). The position offers an opportunity to work with state-of-the-art technology while balancing performance, power, and cost optimizations.
Broadcom offers an excellent benefits package including medical, dental, and vision insurance, 401(k) with company matching, equity opportunities through ESPP, and various leave benefits. The company culture promotes collaboration across internal and customer teams, making it an ideal environment for self-motivated professionals who excel in problem-solving and attention to detail.
This position represents an excellent opportunity for experienced RTL designers looking to work with advanced semiconductor technology at a leading global company. The role combines technical expertise with strategic thinking, as you'll be involved in design management and development methodologies while working with cutting-edge technology nodes.
Responsibilities For High Speed RTL Design Engineer
- Design and develop high-speed DSP SerDes RTL
- Work on equalization, adaptation and high-speed ADC calibration
- Implement Design for test and DFT friendly RTL
- Drive performance, power, and cost optimization over project lifetime
- Work effectively across internal and end customers teams
Requirements For High Speed RTL Design Engineer
- MS or PhD in Electrical Engineering or Computer Engineering
- 6+ years of experience in high speed ADC based SerDes RTL design
- Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes
- Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint
- Deep understanding of high-speed serial interconnect architectures
- Experience in synthesis, CDC, static timing analysis
- Experience in design management
- Strong analytical thinking and problem-solving skills
- Excellent knowledge/experience with TSMC 7nm-2nm
Benefits For High Speed RTL Design Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Annual discretionary bonus
- Equity awards
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