High Speed RTL Design Engineer

Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a High Speed RTL Design Engineer to join their team in San Jose, CA. This is a senior-level position requiring extensive experience in high-speed DSP SerDes RTL design.

The role demands a strong educational background with either an MS or PhD in Electrical Engineering or Computer Engineering, coupled with 6+ years of hands-on experience in high-speed ADC based SerDes RTL design. The ideal candidate will bring expertise in Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes, including sophisticated knowledge of equalization, adaptation, and high-speed ADC calibration.

Key responsibilities include designing and developing high-speed DSP SerDes RTL, working on complex technical challenges involving equalization and adaptation, and ensuring optimal performance metrics. The position requires proficiency with front-end tools such as NCVerilog, NCSIM, Simvision, and Lint, as well as experience in synthesis, CDC, and static timing analysis.

The compensation package is highly competitive, with a base salary range of $120,000 to $192,000, plus eligibility for discretionary annual bonuses and equity compensation. Broadcom offers comprehensive benefits including medical, dental, and vision insurance, 401(k) with company matching, ESPP, and various paid time off options.

This role presents an excellent opportunity for a seasoned RTL design engineer to work with cutting-edge technology at a leading semiconductor company. The position involves collaboration with internal and external stakeholders, requiring strong communication skills and the ability to work effectively in a team environment. The successful candidate will contribute to developing next-generation high-speed serial interconnect architectures and drive innovation in the field.