Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking a Senior RTL Synthesis Engineer to join their team in San Jose, CA. This highly visible role focuses on contributing to connectivity solutions for highly integrated data center products.
The position requires a Master's degree in Electrical or Computer Engineering with 6+ years of experience in Physical design. The ideal candidate will be an expert in Logic/Physical Synthesis, capable of using advanced optimization techniques to generate optimized Gate Level Netlist for Timing, Area, and Power. They will be responsible for debugging timing/area/congestion issues while collaborating with RTL and Physical designers.
Key responsibilities include developing and implementing DFT flow, working with CDC, RDC, and static timing analysis methodologies, and developing automation scripts for design flow. The role involves running Formal Verification checks between RTL and Gate level netlist, debugging various issues, and performing RTL Lint while working with designers on waivers.
The position offers a competitive compensation package ranging from $120,000 to $192,000 annually, plus discretionary bonus and equity opportunities. Broadcom provides comprehensive benefits including medical, dental, and vision insurance, 401(k) with company matching, ESPP, and various paid time off options.
This is an excellent opportunity for a seasoned professional looking to work with cutting-edge technology in data center connectivity solutions. The role requires both technical expertise and collaborative skills, as you'll be working closely with various teams to optimize and verify designs. Broadcom offers a supportive and inclusive work environment, valuing diversity and providing equal opportunities for all qualified candidates.