ASIC Design Engineer, IP, Silicon
Job Description
Google is seeking an ASIC Design Engineer to join their Silicon team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role is integral to the team that pushes boundaries in hardware innovation, specifically working on foundation and chassis IPs for Pixel System on Chips (SoCs).
The position requires deep expertise in RTL design, microarchitecture, and ASIC methodology. You'll be working on critical components including Network on Chip (NoC), Clock, Debug, IPC, and Memory Management Unit (MMU) for Pixel SoCs. The role involves collaboration across multiple disciplines, including architecture, software, verification, power, and timing teams.
As an ASIC Design Engineer, you'll be responsible for delivering high-quality Register-Transfer Level (RTL) implementations that meet strict power, performance, and area goals. The work involves sophisticated technical problem-solving in microarchitecture and low power design methodology, requiring careful evaluation of design options.
The position offers the opportunity to work on products used by millions worldwide, contributing to Google's mission of organizing the world's information and making it universally accessible. You'll be part of a team that combines Google's expertise in AI, Software, and Hardware to create groundbreaking user experiences.
This role is ideal for someone with strong technical skills in RTL design, verification, and ASIC methodology, who enjoys collaborative work and has a passion for pushing the boundaries of hardware development. The position offers the chance to work on cutting-edge technology while contributing to products that have a significant impact on users globally.
Working at Google, you'll be part of a company committed to innovation and excellence, with access to world-class resources and the opportunity to work alongside industry experts. The role offers the chance to shape the future of Google's hardware experiences while working in an environment that values creativity, technical excellence, and collaborative problem-solving.
Responsibilities For ASIC Design Engineer, IP, Silicon
- Participate in test planning and coverage analysis
- Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals
- Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up
- Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks
- Create tools/scripts to automate tasks and track progress
Requirements For ASIC Design Engineer, IP, Silicon
- Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience
- 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology
- 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience with a coding language like Python or Perl
Benefits For ASIC Design Engineer, IP, Silicon
- Equal employment opportunity
- Inclusive work environment
- Global collaboration opportunities
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