ASIC Design For Testability Engineer, Silicon
Job Description
Google is seeking an ASIC Design For Testability Engineer to join their Silicon team, working on custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with software automation, focusing on developing and implementing test methodologies for complex integrated circuits.
The position requires expertise in Design for Testability (DFT) and Design for Debugging (DFD) methodologies, with a strong focus on ASIC development and verification. You'll be working with cutting-edge technology, developing solutions that will be used in products reaching millions of users worldwide.
As part of Google's hardware team, you'll collaborate with various engineering teams, including RTL designers, Physical Design engineers, and Product Engineering teams. Your work will involve developing sophisticated test architectures, automating DFT flows, and ensuring the testability of complex SoC designs.
The role offers the opportunity to work on challenging technical problems at scale, with access to Google's vast resources and innovative technology stack. You'll be contributing to the next generation of Google's hardware experiences, focusing on performance, efficiency, and integration.
This position is ideal for someone with strong technical skills in ASIC design and testing, who is passionate about hardware development and wants to make an impact on Google's consumer products. The role combines hands-on technical work with collaborative team efforts, requiring both deep technical expertise and strong communication skills.
Responsibilities For ASIC Design For Testability Engineer, Silicon
- Work with Design for testing (DFT) engineers, Register-Transfer Level (RTL), Physical Designer Engineers, System on a chip (SoC) DFT and Product Engineering team
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) Architecture with multiple voltage, power domains
- Write scripts to automate the DFT flow
- Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow
- Work with members of the DFT team to deliver two or more Subsystems in a SoC
Requirements For ASIC Design For Testability Engineer, Silicon
- Bachelor's or Master's degree or equivalent practical experience
- 5 years of experience with Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies
- Experience in developing DFT specifications and DFT architecture
- Experience in fault modeling, test standards and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation and verification flow
