ASIC Design for Testability Engineer, Silicon
Description For ASIC Design for Testability Engineer, Silicon
Google is seeking an ASIC Design for Testability Engineer to join their hardware team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position requires a strong background in ASIC design for test, with 5 years of experience in the complete silicon life cycle.
The ideal candidate will work with DFT engineers and collaborate closely with RTL and Physical Designer Engineers. They will be responsible for implementing Subsystem level DFT SCAN and Memory Built-In Self-Test Architecture, handling multiple voltage and power domains. The role involves writing complex scripts for DFT flow automation and developing tests for Production in the Automatic Test Equipment flow.
Key technical requirements include expertise in ATPG, Low Power designs, BIST, JTAG, and IJTAG tools. Experience with DFT EDA tools like Tessent is essential, along with proficiency in scripting languages such as Python or Perl. The position demands knowledge of high-performance design DFT techniques and understanding of SOC cycle flows.
This is an opportunity to be part of Google's innovative hardware team, contributing to products used by millions worldwide. The role offers the chance to work with cutting-edge technology, pushing boundaries in custom silicon solutions. You'll be part of a diverse, multi-disciplined team focused on creating radically helpful experiences through the combination of Google AI, Software, and Hardware.
The position is based in Bengaluru, where you'll work with multi-site teams, requiring excellent communication skills and the ability to collaborate effectively across different disciplines. This role is perfect for someone passionate about hardware innovation and eager to shape the next generation of Google's hardware experiences, focusing on unparalleled performance, efficiency, and integration.
Responsibilities For ASIC Design for Testability Engineer, Silicon
- Work with a team of DFT engineers, working with RTL and Physical Designer Engineers
- Work on Subsystem level DFT SCAN, Memory Built-In Self-Test (MBIST) Architecture with multiple voltage, power domains
- Write basic to complex scripts to automate the DFT flow
- Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC Design for Testability Engineer, Silicon
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience
- 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing
- Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow
- Experience with DFT EDA tools (e.g., Tessent)
- Experience with scripting languages such as Perl or Python
- Experience in DFT for a Complex subsystem with multiple physical partitions
- Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG
- Understanding of the flows - Design, Verification, DFT and PD Phases in a SOC cycle
- Ability to scale DFT, with a focus on minimal area overhead
