ASIC Design Verification Engineer, Machine Learning, Early Career
Description For ASIC Design Verification Engineer, Machine Learning, Early Career
Google is seeking an ASIC Design Verification Engineer to join their Technical Infrastructure team. This role focuses on verifying complex digital designs using SystemVerilog and working closely with design engineers. The position involves building efficient constrained-random verification environments, managing the full verification lifecycle, and ensuring robust testing of Google's custom hardware solutions.
As part of Google's hardware engineering team, you'll be instrumental in designing and building systems that power Google's massive computing infrastructure. Your work will directly impact the hardware that goes into Google's cutting-edge data centers, affecting millions of users worldwide. The role requires expertise in SystemVerilog, verification methodologies like UVM, and strong problem-solving abilities.
The position offers a competitive compensation package including base salary, bonus, equity, and comprehensive benefits. Google's Technical Infrastructure team is proud to be at the forefront of developing and maintaining data centers and building next-generation Google platforms. The team is known for their hands-on approach to engineering and commitment to excellence.
This is an excellent opportunity for someone with verification expertise who wants to work on challenging projects at scale. You'll be part of a team that ensures the reliability and performance of Google's custom hardware solutions, working in a collaborative environment with some of the best engineers in the industry. The role combines technical depth with the opportunity to impact products used by millions of people globally.
Responsibilities For ASIC Design Verification Engineer, Machine Learning, Early Career
- Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For ASIC Design Verification Engineer, Machine Learning, Early Career
- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience
- 1 year of experience coding in SystemVerilog through internships or work experience
- Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs
- Experience with verification methodology such as UVM/OVM/VMM (preferred)
- Experience with the full verification life cycle (preferred)
- Experience in SystemVerilog (preferred)
- Excellent team player, problem-solving, and communication skills (preferred)
Benefits For ASIC Design Verification Engineer, Machine Learning, Early Career
- bonus
- equity
- benefits
