ASIC RTL Engineer III, Silicon
Job Description
Join Google's Platforms and Devices team as an ASIC RTL Engineer III, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering expertise with software integration to create innovative computing experiences. You'll work on designing and implementing RTL for complex digital systems, focusing on high-performance and low-power solutions.
The position requires strong technical skills in digital logic design, RTL development, and hardware verification. You'll be responsible for the complete design cycle from specification to silicon bring-up, working with cutting-edge technology in areas such as memory compression, fabric design, and SOC architecture. The role offers the opportunity to work with multi-disciplined teams across different locations, contributing to products that impact millions of users worldwide.
As part of Google's hardware innovation team, you'll help shape the next generation of computing platforms, combining the best of Google's AI, software, and hardware capabilities. The role provides excellent growth opportunities, working with industry-leading experts and advanced technologies in silicon design.
This position is ideal for someone who has strong fundamentals in hardware design, enjoys solving complex technical challenges, and wants to work on products that push the boundaries of what's possible in consumer technology. You'll be supported by Google's extensive resources and will have the opportunity to influence the direction of future hardware platforms.
Responsibilities For ASIC RTL Engineer III, Silicon
- Define the block-level design document (interface protocol, block diagram, transaction flow, pipeline, etc.)
- Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure, and FPGA/silicon bring-up
- Participate in test plan and coverage analysis of the block and ASIC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For ASIC RTL Engineer III, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 4 years of experience with digital logic design principles, RTL design concepts, and languages like Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques
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