ASIC RTL Integration Engineer
Job Description
Join Google's innovative hardware team as an ASIC RTL Integration Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google AI, Software, and Hardware to create groundbreaking experiences. You'll lead a team of ASIC RTL engineers, focusing on sub-system and chip-level integration activities, while working closely with architecture teams to develop implementation strategies that optimize performance, power, and area (PPA).
The position requires deep expertise in high-performance design and multi-power domains with clocking, along with proven experience in multiple SoCs with silicon success. You'll be responsible for complex feature development, code reviews, and cross-functional collaboration with Verification, Design for Test, Physical Design, and Software teams.
As part of Google's mission to organize the world's information and make it universally accessible, you'll contribute to research, design, and development of new technologies that make computing faster, seamless, and more powerful. This role offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance and efficiency that impacts millions of users worldwide.
The ideal candidate brings strong technical leadership, expertise in ASIC design methodologies, and a comprehensive understanding of chip design flow. You'll work in an environment that values innovation, collaboration, and technical excellence, with the resources and support of one of the world's leading technology companies.
Responsibilities For ASIC RTL Integration Engineer
- Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features
- Interact closely with architecture team and develop implementation strategies to meet quality, schedule and performance, power, and area (PPA) for sub-system/chip-level integration
- Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process
Requirements For ASIC RTL Integration Engineer
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 8 years of experience in high-performance design, multi-power domains with clocking
- Experience in multiple SoCs with silicon success
- Experience with Verilog or System Verilog language
Benefits For ASIC RTL Integration Engineer
- Comprehensive health benefits
- Retirement plans
- Equal opportunity employer
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