ASIC Static Timing Analysis Engineer, Silicon
Description For ASIC Static Timing Analysis Engineer, Silicon
Google is seeking an experienced ASIC Static Timing Analysis Engineer to join their hardware team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position combines hardware expertise with Google's AI and software capabilities to create innovative solutions.
As an ASIC Static Timing Analysis Engineer, you'll be responsible for driving sign-off timing convergence for high-performance designs and establishing comprehensive STA methodologies. You'll work with cutting-edge technology and tools like PrimeTime, Tempus, and DMSA to ensure optimal chip performance.
The role requires deep expertise in silicon timing closure and chip integration, with a focus on STA sign-off constraint authoring and automation. You'll collaborate with block owners and be part of a diverse team that pushes boundaries in hardware development.
Google's mission to organize world's information drives this position, where you'll contribute to developing technologies that make computing faster, seamless, and more powerful. The role offers the opportunity to impact millions of users worldwide through Google's hardware products.
The ideal candidate will have extensive experience in semiconductor device physics, transistor characteristics, and expertise in extraction of design parameters and QoR metrics. This position offers the chance to work on next-generation hardware experiences, delivering unparalleled performance, efficiency, and integration in Google's innovative product lineup.
Responsibilities For ASIC Static Timing Analysis Engineer, Silicon
- Drive the sign-off timing convergence for high performance designs
- Set up timing constraints, defining the overall Static Timing Analysis (STA) methodology
- Set up the STA infrastructure and sign-off convergence flows
- Work with block owners throughout the project for sign-off timing convergence
Requirements For ASIC Static Timing Analysis Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 12 years of experience in silicon timing closure and chip integration
- Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation
- Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using Tweaker, Primeclosure, DMSA
Benefits For ASIC Static Timing Analysis Engineer, Silicon
- Equal opportunity employer
- Accommodation for special needs
