Chipset Power Architect, Devices and Services, Silicon

Google is seeking a Chipset Power Architect to join their Devices and Services Silicon team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position involves leading the definition and optimization of power requirements for Tensor mobile SoCs, focusing on Power-Performance-Area (PPA) optimization under peak current and thermal constraints.

The ideal candidate will have extensive experience in power management and low power design methodology, with a strong background in electrical engineering. They will be responsible for defining power KPIs, leading cross-functional teams, and driving power optimizations from concept to mass production. The role requires expertise in SoC power modeling and analysis, along with a deep understanding of power optimization techniques such as multi Vth/power/voltage domain design, clock gating, and Dynamic Voltage Frequency Scaling.

This is an opportunity to work at the cutting edge of hardware development at one of the world's leading technology companies. The position offers competitive compensation including a base salary range of $183,000-$271,000, plus bonus, equity, and comprehensive benefits. The role is based in either Mountain View or San Diego, California, and involves collaboration with various teams to push the boundaries of hardware innovation.

The successful candidate will play a key role in shaping the next generation of Google's hardware experiences, contributing to products used by millions worldwide. This position requires both technical expertise and strong leadership skills, as you'll be working with cross-functional teams and representing power status to the leadership team.