Chipset Power Architect, Devices and Services, Silicon
Description For Chipset Power Architect, Devices and Services, Silicon
Google is seeking a Chipset Power Architect for their Devices and Services, Silicon team. This role is part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. The ideal candidate will contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences to deliver unparalleled performance, efficiency, and integration.
Key responsibilities include:
- Leading the definition of power requirements for Tensor mobile SoCs
- Defining power Key Performance Indicators and SoC/IP-level power goals
- Modeling system on a chip (SoC) and IP-level power
- Proposing and driving power optimizations throughout the design process
- Conducting power-performance trade-off analysis
The role requires a Bachelor's degree in Electrical Engineering or equivalent practical experience, with 8 years of experience in power management or low power design/methodology. The candidate should have experience with low power architecture, power optimization techniques, and full product delivery cycle.
Preferred qualifications include a Master's or PhD in Electronics or Computer Engineering/Science, experience with SoC power modeling and analysis, knowledge of ASIC design flows, and excellent communication skills.
This position offers a competitive salary range of $177,000-$266,000 + bonus + equity + benefits, determined by factors such as job-related skills, experience, and location. Google is committed to diversity, equal opportunity, and creating a culture of belonging for all employees.
Responsibilities For Chipset Power Architect, Devices and Services, Silicon
- Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints
- Define power Key Performance Indicators and SoC/IP-level power goals, and lead cross-functional architecture, design, implementation and software teams to achieve power goals in volume production
- Model system on a chip (SoC) and IP-level power and perform power rollups
- Propose and drive power optimizations throughout the design process from concept to mass productization
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions and represent status of SoC power to leadership team
Requirements For Chipset Power Architect, Devices and Services, Silicon
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience in power management or low power design/methodology
- Experience with low power architecture and power optimization techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS))
- Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization)
Benefits For Chipset Power Architect, Devices and Services, Silicon
- Bonus
- Equity
- Benefits
