Junior Design Verification Engineer, Networking, Google Cloud
Job Description
Google Cloud is seeking a Junior Design Verification Engineer to join their Networking team. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and cloud platform. As a Design Verification Engineer, you'll work on verification components, constrained-random testing, and system testing for server chip designs. You'll collaborate with design and verification engineers, handling the full verification lifecycle from planning to coverage closure.
The position requires expertise in digital logic verification using SystemVerilog or Specman/E, and you'll be working on cutting-edge hardware solutions that power Google's direct-to-consumer products. The role offers the opportunity to shape the next generation of hardware experiences, focusing on performance, efficiency, and integration.
The ideal candidate should have a strong foundation in electrical engineering or computer science, with experience in verification methodologies and digital design. Knowledge of UVM, SystemVerilog, and scripting languages is highly valued. You'll be part of a team that prioritizes security, efficiency, and reliability while working on projects that impact billions of users worldwide.
This is an excellent opportunity for someone early in their career to join a leading tech company and work on innovative hardware solutions. The role offers exposure to advanced technologies and the chance to work with industry-leading tools and methodologies. You'll be contributing to projects that are essential to Google's infrastructure and cloud services, making a significant impact on the company's hardware capabilities.
Responsibilities For Junior Design Verification Engineer, Networking, Google Cloud
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Apply close coverage measures to identify verification holes and show progress towards tape-out
Requirements For Junior Design Verification Engineer, Networking, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs
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