Junior Design Verification Engineer, Networking, Google Cloud
Job Description
Google Cloud is seeking a Junior Design Verification Engineer to join their Networking team, focusing on developing and verifying digital designs for server chip systems. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on hardware that powers Google's services and Cloud infrastructure. The role involves collaborating with design engineers to create verification components, perform constrained-random testing, and ensure verification closure for digital designs.
You'll be responsible for the complete verification lifecycle, from planning to test execution and coverage closure. The position requires expertise in SystemVerilog or similar verification methodologies, and you'll work with cutting-edge hardware designs that support Google's direct-to-consumer products.
This is an excellent opportunity for early-career professionals to join Google's hardware innovation team, working on projects that impact billions of users worldwide. The role combines technical depth in hardware verification with the chance to shape the future of Google's computing infrastructure.
The position offers the chance to work with industry-leading tools and methodologies while collaborating with experienced engineers in either Tel Aviv or Haifa, Israel. You'll be part of a team that prioritizes security, efficiency, and reliability in developing next-generation computing solutions.
If you're passionate about hardware verification, have a strong foundation in digital design, and want to contribute to Google's technological advancement, this role offers the perfect blend of challenge and growth opportunity in a world-class engineering environment.
Responsibilities For Junior Design Verification Engineer, Networking, Google Cloud
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Apply close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Junior Design Verification Engineer, Networking, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs
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