Lead ASIC DFT Engineer

Google is seeking a Lead ASIC DFT Engineer to join their hardware team in Mountain View, developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced hardware design with Google's cutting-edge AI and software capabilities to create innovative computing experiences.

The position requires deep expertise in Design for Testing (DFT) methodologies, including scan insertion, ATPG, and silicon debug. You'll be responsible for architecting and implementing DFT solutions for complex System on Chip (SoC) designs with multiple voltage and power domains. The role involves both technical leadership and hands-on work, from early architecture phases through to post-silicon validation.

As a Lead Engineer, you'll guide junior team members while taking ownership of DFT implementation across multiple subsystems. The work encompasses developing automated testing solutions, optimizing production test flows, and ensuring robust testability of Google's custom silicon designs. You'll work with state-of-the-art EDA tools and contribute to advancing Google's hardware capabilities.

The compensation package is competitive, ranging from $183,000 to $271,000 base salary, plus bonus, equity, and comprehensive benefits. This is an opportunity to work on cutting-edge hardware projects at scale, with access to Google's vast technical resources and the chance to impact products used by millions of people worldwide.

The ideal candidate will bring 8+ years of relevant experience, strong technical skills in DFT and physical design, and the ability to drive innovation in testing methodologies. Knowledge of modern DFT techniques like Streaming Scan Network and High-Bandwidth IJTAG is highly valued. The role offers the chance to work at the intersection of hardware and software, contributing to Google's next generation of computing products.