Physical Design Flow and Methodology Engineer

Google is seeking a Physical Design Flow and Methodology Engineer to join their ML, Systems, & Cloud AI (MSCA) organization. This role is crucial in shaping the future of AI/ML hardware acceleration, particularly working on TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications.

The position involves developing and implementing automated workflows for physical design Electronic Design Automation (EDA) tools within the Google Compute Engine environment. You'll be responsible for streamlining ASIC physical design workflows, improving team efficiency, and ensuring high-quality results for ASIC tapeouts.

As part of the chip implementation team, you'll work with industry-standard physical design EDA tools and RTL To GDS CAD flows. The role requires expertise in place and route, EM/IR, static timing, and proficiency in scripting languages. You'll collaborate with chip design teams, develop auditing tools, and own end-to-end physical design of blocks and subsystems.

The MSCA organization is responsible for designing, implementing, and managing hardware, software, ML, and systems infrastructure for all Google services and Google Cloud. The work impacts billions of users worldwide and includes developing cutting-edge technologies like TPUs and running global networks.

This is an excellent opportunity for someone passionate about hardware design and automation, offering competitive compensation ($156,000-$229,000 + bonus + equity + benefits) and the chance to work on innovative projects that shape the future of AI/ML hardware acceleration at one of the world's leading technology companies.