Senior Design Verification Engineer, Google Cloud
Job Description
Google Cloud is seeking a Senior Design Verification Engineer to join their Research and Development team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position involves building verification components, performing constrained-random testing, and driving verification closure for digital designs. You'll work closely with design and verification engineers, creating efficient testing environments that thoroughly examine designs through their corner-cases to identify potential issues. The role requires expertise in SystemVerilog, UVM, and formal verification tools, managing the complete verification lifecycle from planning to coverage closure. As part of Google's Technical Infrastructure team, you'll contribute to the architecture that supports Google's entire product portfolio, ensuring optimal performance and reliability. The position offers the opportunity to work on cutting-edge hardware solutions that impact millions of users worldwide, while collaborating with top talent in the field of silicon design and verification.
Responsibilities For Senior Design Verification Engineer, Google Cloud
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools
- Identify and write all types of coverage measures for corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Senior Design Verification Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience with creating and using verification components and environments in standard verification methodology
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs
