Senior SoC and IP Design Engineer, Google Cloud
Job Description
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Senior SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware expertise with cutting-edge technology development, focusing on creating solutions that drive the next generation of Google's hardware experiences.
As part of the team, you'll work on designing and implementing hardware infrastructure that supports all Google services (including Search and YouTube) and Google Cloud. The position requires deep expertise in digital logic design, RTL concepts, and hardware architecture, with a focus on developing high-performance, efficient silicon solutions.
The role involves working with state-of-the-art technology, including TPUs and hyperscale computing infrastructure, while contributing to Google Cloud's Vertex AI platform. You'll be responsible for critical aspects of hardware design, from block-level documentation to RTL coding and verification, requiring both technical expertise and collaborative skills.
This is an excellent opportunity for experienced hardware engineers who want to impact billions of users worldwide while working with cutting-edge technology in cloud computing and artificial intelligence. The position offers the chance to work with multi-disciplined teams across different locations, contributing to Google's next-generation hardware infrastructure.
The ideal candidate will bring strong technical skills in hardware design, experience with various design tools and methodologies, and the ability to optimize for both performance and power efficiency. This role combines the excitement of working on innovative technology with the scale and impact of Google's global infrastructure.
Responsibilities For Senior SoC and IP Design Engineer, Google Cloud
- Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.)
- Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure activities
- Participate in test plan and coverage analysis of the block and SoC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
- Experience with SoC or IP architecture
Benefits For Senior SoC and IP Design Engineer, Google Cloud
- Equal Employment Opportunity
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