Senior SoC and IP Design Engineer, Google Cloud
Job Description
Join Google Cloud's innovative team as a Senior SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, machine learning, and systems infrastructure supporting all Google services and Google Cloud.
You'll be working on ASIC SoC development from POR to Production, focusing on SoC Level micro architecture definitions, RTL coding, and quality assurance. The position requires deep expertise in digital logic design, RTL concepts, and various hardware description languages. You'll collaborate with cross-functional teams in architecture, software, verification, power, timing, and synthesis.
The role offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. You'll be working on projects that impact billions of users worldwide through Google's services and Cloud platform. The team prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing.
As a senior engineer, you'll contribute to both technical implementation and architectural decisions, working with cutting-edge technologies in areas such as PCIe, UCIe, DDR, AXI, and ARM processors. The position requires excellent problem-solving and debugging skills, with opportunities to influence design flow and methodologies.
This is an excellent opportunity for someone passionate about hardware design who wants to make a significant impact on Google's infrastructure and products while working with some of the industry's most advanced technologies and talented engineers.
Responsibilities For Senior SoC and IP Design Engineer, Google Cloud
- Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Participate in architecture feedback
Requirements For Senior SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience in logic design
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with design sign off and quality tools (e.g., Lint, CDC, etc.)
- Experience with SOC architecture
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