Senior SoC and IP Design Engineer, Google Cloud
Job Description
Join Google Cloud's innovative team as a Senior SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. This role combines advanced ASIC design with the opportunity to impact products used by millions worldwide. You'll be part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and Cloud platform.
In this position, you'll leverage your ASIC design expertise to develop SoC from POR to Production, including creating SoC Level micro architecture definitions, RTL coding, and quality assurance. You'll work closely with cross-functional teams in architecture, software, verification, power, timing, and synthesis, tackling technical challenges and optimizing designs for performance, power, and area.
The role offers the chance to contribute to groundbreaking projects, including Google Cloud's Vertex AI platform and the development of TPUs. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. This position requires strong technical skills in digital logic design, RTL development, and SOC architecture, combined with excellent problem-solving abilities.
Working at Google means joining a company that's committed to innovation and technical excellence, while being part of a diverse and inclusive workplace. You'll have the opportunity to shape the future of hardware experiences, delivering unparalleled performance and efficiency in Google's products and services. The position offers the chance to work on cutting-edge technology while collaborating with some of the industry's brightest minds in either Tel Aviv or Haifa, Israel.
Responsibilities For Senior SoC and IP Design Engineer, Google Cloud
- Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Participate in architecture feedback
Requirements For Senior SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience in logic design
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with design sign off and quality tools (e.g., Lint, CDC, etc.)
- Experience with SOC architecture
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