Senior SoC and IP Design Engineer, Google Cloud
Job Description
Join Google Cloud's innovative team as a Senior SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, machine learning, and systems infrastructure supporting all Google services and Google Cloud.
As a Senior SoC and IP Design Engineer, you'll leverage your ASIC design expertise to develop ASIC SoC from POR to Production. Your responsibilities will include creating SoC Level micro architecture definitions, RTL coding, and ensuring RTL quality. You'll work on design flow and methodologies while collaborating with cross-functional teams in architecture, software, verification, power, timing, and synthesis.
The position requires strong technical skills in digital logic design, RTL concepts, and hardware description languages like Verilog or SystemVerilog. You'll be involved in critical aspects of chip development, from architecture definition to silicon bring-up, working on cutting-edge projects that impact billions of users worldwide.
Google Cloud's commitment to security, efficiency, and reliability is paramount, and you'll be contributing to shaping the future of hyperscale computing. The role offers the opportunity to work on advanced technologies, including TPUs and global network infrastructure, while contributing to Google Cloud's Vertex AI platform, which brings Gemini models to enterprise customers.
This is an excellent opportunity for experienced hardware engineers who want to make a significant impact on Google's infrastructure and cloud services, working with state-of-the-art technology and collaborating with world-class engineers in either Tel Aviv or Haifa, Israel.
Responsibilities For Senior SoC and IP Design Engineer, Google Cloud
- Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Participate in architecture feedback
Requirements For Senior SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience in logic design
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with design sign off and quality tools (e.g., Lint, CDC, etc.)
- Experience with SOC architecture
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