Senior SoC Design Verification Engineer, Google Cloud
Description For Senior SoC Design Verification Engineer, Google Cloud
Join Google's Technical Infrastructure team as a Senior SoC Design Verification Engineer, where you'll be instrumental in developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced technical expertise with strategic verification planning to ensure the quality and reliability of Google's hardware innovations. You'll work within a dynamic R&D environment, collaborating with design and verification engineers to build and validate complex digital systems.
Your responsibilities will span the entire verification lifecycle, from initial planning to final coverage closure. You'll utilize industry-standard methodologies and tools, including SystemVerilog and UVM, to create robust verification environments that thoroughly test designs through their corner cases. The role requires deep expertise in digital design verification, particularly for ASICs and FPGAs, and the ability to work closely with cross-functional teams.
As part of Google's server chip design team, you'll contribute to the architecture that powers Google's vast product portfolio. The position offers the opportunity to work on cutting-edge technology that impacts millions of users worldwide, while being part of a team that values innovation and technical excellence. Your work will directly influence the next generation of Google's hardware experiences, focusing on unparalleled performance, efficiency, and integration.
The ideal candidate will bring extensive experience in SoC verification, strong technical skills, and the ability to drive verification closure while maintaining high quality standards. This role offers the chance to work at the forefront of hardware development, contributing to Google's continued leadership in technology innovation.
Responsibilities For Senior SoC Design Verification Engineer, Google Cloud
- Plan the verification of digital design blocks
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Identify and write all types of coverage measures for corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and show progress towards tape-out
Requirements For Senior SoC Design Verification Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 8 years of experience with creating and using verification components and environments in standard verification methodology
- Experience verifying digital systems using standard IP components/interconnects
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs
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