Senior SOC RTL Design Engineer, Google Cloud
Job Description
Google Cloud is seeking a Senior SOC RTL Design Engineer to join their team developing custom silicon solutions that power Google's direct-to-consumer products. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which designs and manages hardware, software, and infrastructure for Google services and Google Cloud.
The position requires expertise in digital logic design, RTL development, and system-on-chip architecture. You'll be working on cutting-edge hardware solutions that require deep technical knowledge in areas such as PCIe, UCIe, DDR, AXI, and ARM processors. The role involves both independent technical work and collaboration with multi-disciplinary teams across different locations.
As a Senior SOC RTL Design Engineer, you'll be responsible for defining system architecture, developing RTL code, performing complex debugging and optimization, and ensuring the quality and performance of hardware designs. The work directly impacts Google's infrastructure and cloud services used by billions of people worldwide.
The ideal candidate should have strong experience in hardware design, verification, and optimization, with particular emphasis on low-power design techniques and high-performance computing. Knowledge of scripting languages like Python or Perl is valuable for automation and tooling development.
This is an excellent opportunity for an experienced hardware engineer to work on challenging technical problems at scale, while contributing to Google's next generation of hardware infrastructure and cloud computing solutions.
Responsibilities For Senior SOC RTL Design Engineer, Google Cloud
- Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with PCIe (PCI)
