Signoff and Circuit Methodology Engineer
Job Description
Google is seeking a Signoff and Circuit Methodology Engineer to join their Platforms and Devices team. This role is crucial in ensuring the reliability and performance of Google's custom-designed machines, which form one of the largest computing infrastructures globally. The position combines hardware engineering with software automation, requiring expertise in physical design, static timing analysis, and circuit methodology.
The role involves working closely with post-silicon validation teams and cross-functional teams to improve and debug various hardware-related issues. You'll be responsible for developing and implementing new circuit methodologies for low-power subsystems and SoCs, while also working with testchip teams on process nodes for custom IP validation and characterization.
As part of Google's Hardware Testing Engineering team, you'll contribute to the R&D lab, designing test equipment for prototypes and developing scalable testing protocols. The position requires a strong background in electrical engineering or computer science, with significant experience in physical design and static timing analysis.
The ideal candidate will have expertise in using Static Timing Analysis (STA) tools, power grid network delivery, and power analysis tools. Experience with automation using TCL, Python, and Perl is highly valued, as is knowledge of speed path debug and correlation studies. This role offers the opportunity to work on cutting-edge hardware technology while being part of a team that combines the best of Google's AI, software, and hardware capabilities.
Responsibilities For Signoff and Circuit Methodology Engineer
- Work with post-silicon validation teams to improve and debug speed, Vmin and yield related issues
- Work with cross-functional teams circuit design, physical design and sign-off methodology teams
- Explore and specify new circuit/Static Timing Analysis methodologies for better polycrystalline silicon photovoltaic modules
- Work with the testchip teams on process nodes to build, validate and characterize custom Internet Protocols (IPs)
- Build automation for circuit methodology, simulation and analysis
Requirements For Signoff and Circuit Methodology Engineer
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 5 years of experience in physical design
- 5 years of experience in static timing analysis, circuit/signoff methodology and simulation
- Experience in one or more sign-off convergence in Static timing analysis (STA) electrical checks and physical verification domains
