Signoff and Design Methodology Engineer, Silicon
Job Description
Join Google's innovative hardware team as a Signoff and Design Methodology Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced technical expertise in chip design with the opportunity to impact products used by millions worldwide. You'll be working with state-of-the-art technology, focusing on mobile System on Chip (SoC) design and optimization.
The position requires deep expertise in static timing analysis, synthesis, and physical design automation. You'll be responsible for driving sign-off timing methodologies, analyzing power performance area trade-offs, and working closely with cross-functional teams including architecture, IPs, design, and power methodology teams. The role involves collaboration with foundry partners to refine signoff methodology for improved convergence and yield.
As part of Google's hardware team, you'll contribute to the company's mission of organizing the world's information and making it universally accessible. The team combines Google's strengths in AI, Software, and Hardware to create groundbreaking experiences. Your work will directly influence the next generation of hardware experiences, focusing on unparalleled performance, efficiency, and integration.
This is an excellent opportunity for someone with strong technical skills in chip design and methodology who wants to work on cutting-edge technology at scale. You'll be part of a team that pushes boundaries and innovates in the hardware space, with the backing of Google's resources and reach. The role offers the chance to work on meaningful projects that impact millions of users while advancing the state of the art in silicon design and methodology.
Responsibilities For Signoff and Design Methodology Engineer, Silicon
- Drive the sign-off timing methodologies for mobile System on a chip (SoCs) to push Power Performance Area (PPA) and yield
- Analyze power performance area trade-offs across different methodologies and technologies
- Work on prototyping of subsystems to deliver optimized PPA recipes
- Work with cross-functional architecture, Internet Protocols (IPs), design, power and sign-off methodology teams
- Work with foundry to refine signoff methodology to improve convergence and yield
Requirements For Signoff and Design Methodology Engineer, Silicon
- Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience
- 5 years of experience with static timing analysis, synthesis, physical design & automation
- Experience in physical design tool automation such as synthesis, P&R and sign-off tools
- Knowledge of timing constraints, convergence and signoff
- Knowledge of parasitic extraction tools and flow
- Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog)
- Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies
