Silicon Micro-architecture and RTL Lead
Job Description
Google Cloud is seeking a Silicon Micro-architecture and RTL Lead to shape the future of AI/ML hardware acceleration. This role focuses on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. As part of the Technical Infrastructure team, you'll be instrumental in developing custom silicon solutions that power Google's TPU future.
The position involves working with complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems. You'll collaborate closely with various teams including architecture, verification, power and performance, and physical design to deliver high-quality designs for next-generation data center accelerators.
This is a senior technical role where you'll be responsible for solving complex technical problems through innovative micro-architecture and practical logic solutions. You'll need to evaluate design options considering complexity, performance, power, and area constraints. The role requires deep expertise in ASIC development, micro-architecture design, and system integration.
Working at Google's Bengaluru design organization, you'll lead a team of engineers in developing complex IPs and Subsystems. The role offers the opportunity to work on technology that powers products used by millions worldwide, while pushing the boundaries of what's possible in AI/ML hardware acceleration.
The ideal candidate will bring extensive experience in ASIC development, strong leadership skills, and a deep understanding of hardware architecture. This role offers the chance to make significant contributions to Google's AI infrastructure while working with cutting-edge technology in a collaborative environment.
Responsibilities For Silicon Micro-architecture and RTL Lead
- Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization
- Own micro-architecture and implementation of IPs and subsystems
- Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive Power, Performance and Area improvements for the domains owned
Requirements For Silicon Micro-architecture and RTL Lead
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL)
- Experience in micro-architecture and design IPs and Subsystems
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience with scripting languages (e.g., Python or Perl)
- Experience in SoC designs and integration flows
- Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies
- Knowledge of high performance and low power design techniques
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