Silicon RTL Design Engineer Networking, Google Cloud
Job Description
Join Google's Technical Infrastructure team as a Silicon RTL Design Engineer working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. In this role, you'll be instrumental in developing custom silicon solutions that drive the future of Google's TPU architecture and its integration within AI/ML systems.
You'll work on accelerating and improving traffic efficiency in data centers, collaborating closely with cross-functional teams in architecture, verification, power and performance, and physical design. Your responsibilities will include developing next-generation data center accelerators, solving technical challenges through innovative micro-architecture and practical logic solutions, and evaluating design options with a focus on complexity, performance, power, and area optimization.
As part of Google's Technical Infrastructure team, you'll contribute to the backbone that makes Google's product portfolio possible. The team takes pride in being the engineers' engineers, working on everything from developing and maintaining data centers to building next-generation Google platforms. Your work will directly impact millions of users worldwide by ensuring optimal network performance and user experience.
This position offers an exciting opportunity to shape the future of AI/ML hardware acceleration at Google, working with state-of-the-art technology and collaborating with industry experts. You'll be part of a team that values innovation, technical excellence, and practical problem-solving, while contributing to products that have global impact.
Responsibilities For Silicon RTL Design Engineer Networking, Google Cloud
- Own microarchitecture and implementation of IPs and subsystems in the Networking domain
- Work with design team members to close feature definitions and develop microarchitecture specifications
- Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Work on Power, Performance and Area improvements for the domains owned
Requirements For Silicon RTL Design Engineer Networking, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience in micro-architecture and design of IPs and Subsystems
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
Related Jobs
