Silicon Subsystems RTL Design Engineer, Google Cloud
Job Description
Join Google Cloud as a Silicon Subsystems RTL Design Engineer and shape the future of AI/ML hardware acceleration. This role focuses on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of an innovative team developing custom silicon solutions for Google's TPU platform, contributing to products used by millions worldwide.
Working in the ML, Systems, & Cloud AI (MSCA) organization, you'll collaborate with architecture, verification, power and performance, and physical design teams to deliver next-generation data center accelerators. The role involves solving complex technical problems through innovative micro-architecture and logic solutions, while considering factors like complexity, performance, power, and area optimization.
You'll be responsible for the microarchitecture and implementation of critical subsystems, working closely with Architecture, Firmware, and Software teams. The position requires expertise in ASIC development, design verification, and subsystem design, with opportunities to drive methodology improvements and quality initiatives.
This is an excellent opportunity for experienced engineers passionate about hardware acceleration and AI/ML technologies. You'll work at the forefront of TPU development, contributing to Google's infrastructure that powers services used by billions of people. The role offers the chance to impact the future of hyperscale computing while working with cutting-edge technology in a collaborative environment.
Responsibilities For Silicon Subsystems RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of subsystems in the data center domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Perform Quality check flows like Lint, CDC, RDC, VCLP
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area improvements for the domains owned
Requirements For Silicon Subsystems RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of subsystems
