SoC DFT Engineer, Google Cloud
Job Description
Google Cloud is seeking a System on a Chip (SoC) Design for Test (DFT) Engineer to join their ML, Systems, & Cloud AI (MSCA) organization. This role is crucial in defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. The position involves working on custom silicon solutions that power Google's direct-to-consumer products, contributing to hardware innovations used by millions worldwide.
The role sits within Google's MSCA organization, which is responsible for designing and managing hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. The team prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing, including work on TPUs and global network infrastructure.
As a DFT Engineer, you'll be responsible for defining silicon test strategies, creating DFT specifications for next-generation SoCs, and working closely with test engineers for post-silicon debugging. The position requires expertise in DFT methodologies, verification, and industry-standard tools, with a focus on implementing comprehensive test architectures for complex silicon designs.
This is an excellent opportunity for someone passionate about hardware design and testing, offering the chance to work on cutting-edge technology that powers Google's infrastructure and cloud services. The role combines technical expertise with strategic thinking, requiring both hands-on engineering skills and the ability to architect complex test solutions.
Responsibilities For SoC DFT Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT)
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks
- Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC DFT Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience in DFT specification, definition, architecture, and insertion
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