SoC DFT Engineer, Google Cloud
Job Description
Google Cloud is seeking a System on a Chip (SoC) Design for Test (DFT) Engineer to join their team in developing custom silicon solutions. This role is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for designing and implementing hardware, software, and machine learning infrastructure for Google services and Google Cloud.
The position involves defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You'll be responsible for creating DFT specifications, defining silicon test strategies, and architecting DFT solutions for next-generation SoCs. The role requires collaboration with test engineers for post-silicon debugging and validation.
As part of Google's hardware team, you'll contribute to innovations that power Google's direct-to-consumer products, working on solutions that deliver unparalleled performance, efficiency, and integration. The impact of your work will extend to billions of users worldwide through Google's services and Cloud platform.
The MSCA organization prioritizes security, efficiency, and reliability across all initiatives, from developing TPUs to managing global networks. This team plays a crucial role in shaping the future of hyperscale computing and supports critical platforms like Google Cloud's Vertex AI, which brings Gemini models to enterprise customers.
This is an excellent opportunity for someone with strong DFT expertise who wants to work on cutting-edge technology at scale, contributing to products that have global impact while being part of a team that pushes the boundaries of hardware innovation.
Responsibilities For SoC DFT Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT)
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks
- Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC DFT Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience in DFT specification, definition, architecture, and insertion
Related Jobs
