FPGA Verification Engineer

Hudson River Trading (HRT) is seeking an experienced FPGA verification engineer to join their hardware team. The role involves creating ultra-low latency products for trading on global markets. The ideal candidate should be skilled in writing testbenches, building verification environments, and exercising complex hardware. This position is part of an innovative hardware team integral to HRT's trading success.

Key responsibilities include:

• Creating testbenches and tests for FPGA platforms
• Writing detailed verification plans
• Quickly root-causing RTL bugs
• Collaborating with designers for rapid project bringup and debugging
• Managing regression and continuous integration infrastructure
• Developing and improving open-source and internal tools

Qualifications:

• Excellent debug and analytical skills
• Strong background (4+ years) in RTL functional verification for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Experience with Python
• Comfortable in a Linux environment
• Familiarity with Verilator and/or Cocotb preferred
• Experience with networking protocols preferred
• C++ experience is a plus
• Bachelor's degree in Computer or Electrical Engineering or related field

HRT offers a competitive compensation package, including an annual base salary range of $150,000 to $200,000, potential sign-on and performance bonuses, and company-paid benefits. The company values diversity and maintains a culture of openness, transparency, and togetherness, encouraging great ideas from both veterans and new hires.