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Design Verification Engineer (University Grad)

Meta builds technologies that help people connect, find communities, and grow businesses, including apps like Facebook, Messenger, Instagram, and WhatsApp.
$114,000 - $133,000
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
AR/VR · AI

Description For Design Verification Engineer (University Grad)

Meta Reality Labs (RL) is seeking a Design Verification Engineer to join their cutting-edge AR/VR team. This role sits at the intersection of hardware and software, focusing on custom silicon development for augmented reality devices. As part of Meta's vision to blend real and virtual worlds, you'll work with world-class researchers and engineers to validate new core IP implementations and contribute to state-of-the-art graphics and sensing algorithms.

The position offers an exciting opportunity for university graduates to work on breakthrough technologies in computer vision, machine learning, mixed reality, graphics, displays, and sensors. You'll be responsible for implementing testing infrastructure, creating test bench requirements, and ensuring the quality of various IP modules through comprehensive verification processes.

Working at Meta Reality Labs means being part of a team that's pushing the boundaries of what's possible in AR/VR technology. You'll collaborate with cross-functional teams, including researchers, architects, and designers, to ensure the highest design quality for next-generation AR devices. The role combines technical expertise in verification methodologies with the excitement of working on products that will fundamentally change how we interact with technology.

The compensation package includes a competitive base salary range of $114,000-$133,000, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for someone passionate about hardware verification who wants to make a direct impact on the future of augmented reality technology. The role offers significant growth potential and the chance to work with cutting-edge technology at one of the world's leading tech companies.

Last updated an hour ago

Responsibilities For Design Verification Engineer (University Grad)

  • Work with researchers and architects defining verification plans for each of the different core IP
  • Define and track detailed test plans for the different modules and top levels
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies

Requirements For Design Verification Engineer (University Grad)

Python
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Experience with ASIC development cycle
  • Experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
  • Experience in SystemVerilog Assertions, Formal, Emulation
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
  • Experience in architecting and implementing Design Verification infrastructure
  • Interpersonal experience: cross-group and cross collaboration
  • Must obtain work authorization in country of employment

Benefits For Design Verification Engineer (University Grad)

Medical Insurance
Dental Insurance
Vision Insurance
401k
Equity
  • Medical Insurance
  • Dental Insurance
  • Vision Insurance
  • 401k
  • Equity

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