Design Verification Engineer 2

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world.
Backend
Mid-Level Software Engineer
Hybrid
5,000+ Employees
3+ years of experience
AI

Description For Design Verification Engineer 2

Microsoft's Silicon team builds custom silicon for diverse systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. The AISoC (Artificial Intelligence System on Chip) Silicon team is seeking a passionate Design Verification Engineer to deliver premium-quality designs. This role involves working with cutting-edge custom IP and SoC designs that perform complex and high-performance functions efficiently.

The position requires expertise in design verification with a focus on complex CPU or SoC IP's. You'll be responsible for creating and enhancing verification environments using SystemVerilog and UVM, developing tests, and ensuring functional correctness of designs. The role combines technical depth in computer architecture with practical verification skills.

Microsoft offers a collaborative environment where employees come together with a growth mindset to innovate and achieve shared goals. The company's mission is to empower every person and organization on the planet to achieve more, fostering a culture of inclusion, respect, and accountability.

Working in the dynamic Microsoft AISoC Silicon team, you'll have the opportunity to work on cutting-edge technical projects, interact with architecture and design engineers, and contribute to delivering functionally correct designs for complex systems. The role offers comprehensive benefits including industry-leading healthcare, educational resources, savings and investments options, and generous time away.

This position offers significant growth potential in a rapidly evolving field of custom silicon design, particularly in AI systems. You'll be at the forefront of developing verification solutions for next-generation computing architectures while working with a team of experienced professionals in a supportive environment that values innovation and technical excellence.

Last updated 16 days ago

Responsibilities For Design Verification Engineer 2

  • Plan the verification of complex design IP/SoC interacting with architecture and design engineers
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM
  • Develop tests using UVM or C/C++
  • Analyse and debug test failures with designers to deliver functionally correct design
  • Identify and write functional coverage for stimulus and corner cases
  • Close coverage to plug verification holes and meet tape out requirements

Requirements For Design Verification Engineer 2

Python
  • 3 or more years of experience in design verification with proven track record of delivering complex CPU or SoC IP's
  • Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments
  • Good understanding of computer architecture
  • Substantial background in debugging RTL (Verilog) designs and simulation/emulation environments
  • Scripting language such as Python or Perl

Benefits For Design Verification Engineer 2

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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