Senior Design Verification Engineer
Job Description
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Senior Design Verification Engineer to join their team developing cutting-edge AI components and custom IP solutions. This role combines hardware engineering expertise with software development, focusing on pre-silicon verification of complex ASIC and SOC designs.
The position offers an opportunity to work on Microsoft's expanding Cloud Infrastructure, which powers over 200 online businesses including Azure, Office 365, Xbox Live, and Teams. You'll be leading verification efforts for AI components and custom IP development, working with state-of-the-art hardware designs and verification methodologies.
As a Senior Design Verification Engineer, you'll collaborate with architecture and design teams, develop UVM components, and ensure implementation meets both architectural and micro-architectural intent. The role requires expertise in verification principles, debug techniques, and industry-standard protocols like AMBA AXI.
The position offers competitive compensation ranging from $119,800 to $234,700 USD annually (higher in SF Bay Area and NYC), along with comprehensive benefits including healthcare, educational resources, and parental leave. This hybrid role allows up to 50% work from home, providing flexibility while maintaining collaborative opportunities.
Microsoft's commitment to diversity, inclusion, and professional growth makes this an ideal opportunity for experienced verification engineers looking to impact the future of cloud and AI infrastructure. The role combines technical leadership with hands-on development, requiring both deep technical expertise and strong collaborative skills.
Responsibilities For Senior Design Verification Engineer
- Establish yourself as an integral member of a design verification team for AI components
- Lead a pre-silicon verification team for custom IP and Subsystem components
- Collaborate with architecture and design teams
- Write, execute, enhance, and debug constrained random stimulus
- Develop UVM components to interface between test code and verification environments
- Apply Agile development methodologies
- Provide technical leadership through mentorship and teamwork
- Demonstrate Microsoft core values
Requirements For Senior Design Verification Engineer
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
- 4+ years of industry experience in design verification with delivering complex ASIC or SOC
- Experience with IP/SOC verification for a full product cycle
- Experience of working on AI/Machine Learning (ML) SoCs
- In-depth knowledge of verification and debug principles, testbenches, UVM or C based test environments
- Working knowledge of writing assertions, coverage and/or formal verification
- Knowledge of industry standard bus interfaces such as AMBA AXI protocols
- Background in debugging RTL (Verilog) designs
- Scripting languages such as Zsh, Bash, Python or Perl
- Proficient communication, collaboration and teamwork skills
Benefits For Senior Design Verification Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
